Conventional memory architectures and technologies, such as those including dynamic random access memory (“DRAM”) cells and Flash memory cells, typically are not well-suited to resolve issues of manufacturing and operating resistance change-based memory cells. The above-described memory architectures, while functional for their specific technologies, fall short of being able to adequately address the issues of cycling endurance of resistance-based memory elements and the degradation due to repeated program-erase cycles. As the structures of conventional memory cells differ from resistance-based memory elements, there are different requirements and approaches to improve the reliability (e.g., cycling endurance) of two-terminal resistance-based memory elements.
In certain conventional approaches to forming resistance-based memory elements, materials providing mobile ions have been formed on multiple layers to form a reservoir of ions used in transport to another material for modifying the resistance of the memory cell. Typically, the multiple layers are formed with identical materials and compositions and cooperate to operate as an ionic conductor and an electronic insulator. While functional, there are certain performance deficiencies associated with this structure.
FIG. 1 depicts sub-optimal performance characteristics associated with a conventional multi-layered structure material operable as an ionic conductor and an electronic insulator. Diagram 100 depicts various magnitudes of current I through a memory cell over a number of program-erase cycles, the memory cell being formed with a material operable as an ionic conductor and an electronic insulator. As shown, the magnitudes of current I alternate between a first magnitude 110 associated with an erasing operation and a second magnitude 112 associated with a programming operation. Over a number of cycles 120, the conventional multi-layered structure has its performance characteristics degrade or other otherwise change. In this case, the current “drifts” lower in magnitudes over number of cycles 120 such that an average current magnitude 102 between magnitudes 110 and 112 decreases over a number of program-erase cycles. Typically, additional circuitry (e.g., sense amp circuitry) and resources are required to accommodate or filter out the current drift, especially when sensing a current representative of a data value, such as a read current generated by application of a read voltage during a read operation to a memory cell, for example. Further, the differences in magnitudes between first magnitudes 110 and second magnitudes 112 decrease during a number of cycles 122, which are subsequent in time to the number of cycles 120. In some cases, the phenomena depicted during number of cycles 120 can arise after, for example 10,000 program-erase cycles.
It would be desirable to provide improved systems, integrated circuits, and methods that minimize one or more of the drawbacks associated with conventional techniques for facilitating improved cycling endurance and memory effects for two-terminal resistance-based memory elements disposed in, for example, cross-point arrays or other memory structures suitable for two-terminal resistance-based memory elements.
Although the above-described drawings depict various examples of the invention, the invention is not limited by the depicted examples. It is to be understood that, in the drawings, like reference numerals designate like structural elements. Also, it is understood that the drawings are not necessarily to scale.